Research
We develop thermal metrology and heat-transport engineering for next-generation integrated circuits, spanning high-thermal-conductivity materials, heterogeneous interfaces and bonding, and three-dimensional thermal tomography of interconnects.
Research vision
As chip power density, integration density, and reliability requirements keep rising, heat transport across materials, interfaces, interconnects, and package structures becomes a central constraint for performance and lifetime.
Our research connects experimental thermal metrology — TDTR, FDTR, and Raman mapping — with materials growth, interface engineering, and physical modeling, targeting the structures that matter in real devices: diamond and SiC heat spreaders, bonded interfaces, and 3D-stacked interconnect layers.
High-thermal-conductivity heat-spreading materials
We grow and engineer wide-bandgap heat-spreading materials — diamond, 3C-SiC, and AlN — and tailor their thermal properties for integration with real devices.
Combining epitaxial growth, precision thermal metrology (TDTR / FDTR / Raman mapping), and theory, we turn grain size, doping, and interface structure into designable knobs for heat dissipation.
- Wafer-scale single-crystal 3C-SiC with record in-plane and cross-plane thermal conductivity (Nat. Commun. 2022)
- SiC polytype boundaries with thermal boundary conductance above 2000 MW/m²·K — the highest reported to date
- Low-temperature (<450 °C) BEOL-compatible diamond integrated on GaN transistors, cutting device temperature by 111 °C at 24 W/mm
- B- and N-doped 3C-SiC with the largest thermal-conductivity tunability among common semiconductors
- AlN films with intrinsic room-temperature thermal conductivity up to 321 W/m·K
Heterogeneous interfaces and bonding
Interfaces often dominate the thermal resistance of integrated devices. We study how atoms bond across them — and how to make bonded interfaces thermally transparent.
Using surface-activated bonding (SAB), annealing, and atomically engineered interlayers, we maximize thermal boundary conductance at semiconductor–semiconductor and semiconductor–dielectric interfaces, while revealing the underlying phonon physics with STEM-EELS, Raman spectroscopy, and machine-learned molecular dynamics.
- Room-temperature GaN–diamond SAB bonding with 90 MW/m²·K interface thermal conductance (ACS Appl. Mater. Interfaces 2020)
- Annealing-boosted GaN–diamond interface thermal conductance with a nearly 300% improvement (Adv. Electron. Mater. 2025)
- AlN–SiC interface thermal conductance up to 800 MW/m²·K (arXiv:2602.13827)
- GaN-on-diamond with a high-thermal-conductivity 3C-SiC interlayer relieving thermal-expansion mismatch (Small 2024)
- From elastic phonon transmission at ideal Al–Al₂O₃ interfaces to interface phonon modes in Si–Ge — the physics that guides better bonding (Nat. Commun. 2020, 2021)
Advanced interconnects and 3D thermal tomography
Inside stacked chips, the interconnect stack is a thermal black box. We have developed 3D thermal tomography that experimentally maps the thermal-conductivity distribution of real interconnect layers, from 28 nm down to 3 nm process nodes.
Combining P-FIB staircase preparation, aluminum sensor layers, and layer-by-layer TDTR scanning, we quantify how grain size, diffusion barriers, and interface resistance set the thermal bottleneck — and apply the same metrology to assess dielectric interface quality in hybrid bonding.
- First experimental measurement of 3D thermal-conductivity distribution in interconnect layers across 3–28 nm logic nodes (IEEE IEDM 2025, IEEE EDTM 2026)
- Layer-by-layer thermal maps revealing ultra-low conductivity of nanoscale interconnect layers and the dominant role of thermal boundary resistance (ACS Nano 2026)
- Three-dimensional TDTR scans exposing circuit-pattern effects on heat flow in production interconnect stacks
- Thermal boundary conductance above 150 MW/m²·K as a metric for dielectric interface quality in hybrid bonding (Appl. Phys. Lett. 2026)